A variety of techniques are used to stack packaged integrated circuits. Some methods require special packages, while other techniques stack conventional packages. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits.
One major package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages have recently gained market share.
One family of alternative packages is identified generally by the term “chip scale packaging” or CSP. These differ from leaded packages in that the CSP packages provide connection to an integrated circuit through a set of contacts (often embodied as “bumps,” “spheres,” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package.
The goal of CSP is to occupy as little area as possible and, preferably, approximately the area of the encapsulated IC. Therefore, CSP contacts do not typically extend beyond the outline perimeter of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
CSP has enabled reductions in size and weight parameters for many applications. CSP is a broad category that can include a variety of packages from larger than chip scale to die-sized packages such as the die-sized ball grid array (DSBGA) described in proposed JEDEC standard 95-1 for DSBGA.
To meet the continuing demands for cost and form factor reduction with increasing memory capacities, CSP technologies that aggregate integrated circuits in CSP technology have recently been developed. For example, Sharp, Hitachi, Mitsubishi and Intel recently undertook support of what are called the S-CSP specifications for flash and SRAM applications. Those S-CSP specifications describe, however, stacking multiple die within a single chip scale package and do not provide a technology for stacking chip scale packages. Stacking integrated circuits within a single package requires specialized technology that includes reformulation of package internals and significant expense with possible supply chain vulnerabilities.
There are several known techniques for stacking packages articulated in chip scale technology. The assignee of the present invention has developed previous systems for aggregating FBGA packages in space saving topologies. The assignee of the present invention has systems for stacking BGA packages on a DIMM in a RAMBUS environment.
In U.S. Pat. No. 6,205,654 B1, owned by the assignee of the present invention, a system for stacking ball grid array packages that employs lead carriers to extend connectable points out from the packages is described. Other known techniques add structures to a stack of BGA-packaged ICs. Still others aggregate CSPs on a DIMM with angular placement of the packages. Such techniques provide alternatives, but require topologies of added cost and complexity.
U.S. Pat. No. 6,262,895 Bi to Forthun (the “Forthun patent”) purports to disclose a technique for stacking chip scale packaged ICs. The Forthun patent discloses a “package” that exhibits a flex circuit wrapped partially about a CSP. The flex circuit is said to have pad arrays on upper and lower surfaces of the flex.
The flex circuit of the Forthun “package” has a pad array on its upper surface and a pad array centrally located upon its lower surface. On the lower surface of the flex there are third and fourth arrays on opposite sides from the central lower surface pad array. To create the package of Forthun, a CSP contacts the pad array located on the upper surface of the flex circuit. As described in the Forthun patent, the contacts on the lower surface of the CSP are pushed through “slits” in the upper surface pads and advanced through the flex to protrude from the pads of the lower surface array and, therefore, the bottom surface of the package. Thus, the contacts of the CSP serve as the contacts for the package. The sides of the flex are partially wrapped about the CSP to adjacently place the third and fourth pad arrays above the upper major surface of the CSP to create from the combination of the third and fourth pad arrays, a fifth pad array for connection to another such package. Thus, as described in the Forthun disclosure, a stacked module of CSPs created with the described packages will exhibit a flex circuit wrapped about each CSP in the module.
Most previous known methods for stacking aggregate similarly packaged integrated circuits. What is needed are methods and structures for stacking dissimilar packages and circuits in thermally efficient, reliable structures.